/* sysclock.c */
/*
This file is part of the OpenARMWare.
Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see .
*/
#include
#include "hw_regs.h"
#include "sysclock.h"
#define CRYSTAL_FREQ 16000000UL
#define CRYSTAL_CODE 0x15 /* 16 MHz */
#define PIOSC_FREQ 16000000UL
void sysclk_set_rawclock(void){
uint32_t tmp_rcc;
tmp_rcc = 0; //HW_REG(SYSCTL_BASE+RCC_OFFSET);
tmp_rcc &= ~(_BV(RCC_IOSCDIS) | _BV(RCC_MOSCDIS) | _BV(RCC_USESYSDIV));
tmp_rcc |= _BV(RCC_BYPASS) | _BV(RCC_PWRDN);
tmp_rcc &= ~(3<>RCC2_OSCSR2)&0x07];
}
if(rcc2&_BV(RCC2_DIV400)){
divider = ((rcc2>>RCC2_SYSDIV2LSB)&0x7F)+1;
}else{
divider = ((rcc2>>RCC2_SYSDIV2)&0x3F)+1;
}
}else{
/* use RCC */
if(rcc1&_BV(RCC_BYPASS)){
basefreq = bypass_freq[(rcc1>>RCC_OSCSRC)&0x03];
}
divider = ((rcc1>>RCC_SYSDIV)&0xf)+1;
}
return basefreq/divider;
}