140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/* startup.c */
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/*
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This file is part of the OpenARMWare.
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Copyright (C) 2010 Daniel Otte (daniel.otte@rub.de)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#define RAM_START 0x20000000
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#define RAM_SIZE (96*1024)
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int main(void);
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void uart0_isr(void);
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/* the following are defined by the linker */
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extern char _text;
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extern char _text_end;
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extern char _data;
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extern char _data_end;
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extern char _bss;
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extern char _bss_end;
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typedef void(*isr_fpt)(void);
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static void fault_isr(void){
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for(;;){
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}
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}
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static void default_isr(void){
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for(;;){
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}
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}
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static void nmi_isr(void){
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for(;;){
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}
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}
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void reset_isr(void){
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memcpy(&_data, &_text_end, &_data_end - &_data);
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memset(&_bss, 0, &_bss_end - &_bss);
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main();
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}
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isr_fpt isr_vector[] __attribute__ ((section(".isr_vectors"))) = {
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(isr_fpt)(RAM_START+RAM_SIZE-4),
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reset_isr, /* Reset */
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nmi_isr, /* Non-Maskable Interrupt (NMI) */
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fault_isr, /* Hard Fault */
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default_isr, /* Memory Management */
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fault_isr, /* Bus Fault */
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fault_isr, /* Usage Fault */
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NULL, /* Reserved */
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NULL, /* Reserved */
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NULL, /* Reserved */
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NULL, /* Reserved */
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default_isr, /* SVCall */
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default_isr, /* Debug Monitor */
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NULL, /* Reserved */
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default_isr, /* PendSV */
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default_isr, /* SysTick */
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default_isr, /* GPIO Port A */
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default_isr, /* GPIO Port B */
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default_isr, /* GPIO Port C */
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default_isr, /* GPIO Port D */
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default_isr, /* GPIO Port E */
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uart0_isr, /* UART0 */
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// default_isr, /* UART0 */
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default_isr, /* UART1 */
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default_isr, /* SSI0 */
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default_isr, /* I2C0 */
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NULL, /* Reserved */
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NULL, /* Reserved */
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NULL, /* Reserved */
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NULL, /* Reserved */
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NULL, /* Reserved */
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default_isr, /* ADC0 Sequence 0 */
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default_isr, /* ADC0 Sequence 1 */
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default_isr, /* ADC0 Sequence 2 */
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default_isr, /* ADC0 Sequence 3 */
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default_isr, /* Watchdog Timers 0 and 1 */
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default_isr, /* Timer 0A */
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default_isr, /* Timer 0B */
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default_isr, /* Timer 1A */
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default_isr, /* Timer 1B */
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default_isr, /* Timer 2A */
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default_isr, /* Timer 2B */
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default_isr, /* Analog Comparator 0 */
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default_isr, /* Analog Comparator 1 */
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default_isr, /* Analog Comparator 2 */
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default_isr, /* System Control */
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default_isr, /* Flash Memory Control */
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default_isr, /* GPIO Port F */
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default_isr, /* GPIO Port G */
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default_isr, /* GPIO Port H */
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default_isr, /* UART2 */
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default_isr, /* SSI1 */
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default_isr, /* Timer 3A */
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default_isr, /* Timer 3B */
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default_isr, /* I2C1 */
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NULL, /* Reserved */
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default_isr, /* CAN0 */
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default_isr, /* CAN1 */
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NULL, /* Reserved */
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default_isr, /* Ethernet Controller */
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default_isr, /* Hibernation Module */
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default_isr, /* USB */
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NULL, /* Reserved */
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default_isr, /* µDMA Software */
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default_isr, /* µDMA Error */
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default_isr, /* ADC1 Sequence 0 */
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default_isr, /* ADC1 Sequence 1 */
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default_isr, /* ADC1 Sequence 2 */
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default_isr, /* ADC1 Sequence 3 */
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default_isr, /* I2S0 */
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default_isr, /* EPI */
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default_isr, /* GPIO Port J */
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NULL, /* Reserved */
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};
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