102 lines
3.1 KiB
C
102 lines
3.1 KiB
C
/* sysclock.c */
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/*
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This file is part of the OpenARMWare.
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Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include "hw_regs.h"
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#include "sysclock.h"
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#define CRYSTAL_FREQ 16000000UL
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#define CRYSTAL_CODE 0x15 /* 16 MHz */
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#define PIOSC_FREQ 16000000UL
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void sysclk_set_rawclock(void){
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volatile uint32_t tmp_rcc;
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tmp_rcc = 0; //HW_REG(SYSCTL_BASE+RCC_OFFSET);
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tmp_rcc &= ~(_BV(RCC_IOSCDIS) | _BV(RCC_MOSCDIS) | _BV(RCC_USESYSDIV));
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tmp_rcc |= _BV(RCC_BYPASS) | _BV(RCC_PWRDN);
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tmp_rcc &= ~(3<<RCC_OSCSRC);
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tmp_rcc |= (0<<RCC_OSCSRC);
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HW_REG(SYSCTL_BASE+RCC_OFFSET) = tmp_rcc;
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// tmp_rcc |= _BV(RCC_PWRDN);
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HW_REG(SYSCTL_BASE+RCC_OFFSET) = tmp_rcc;
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HW_REG(SYSCTL_BASE+RCC2_OFFSET) &= ~(_BV(31));
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}
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void sysclk_mosc_verify_enable(void){
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HW_REG(SYSCTL_BASE+MOSCCTL_OFFSET) |= 1; // turn on main oscillator verify circuit
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}
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void sysclk_mosc_verify_disable(void){
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HW_REG(SYSCTL_BASE+MOSCCTL_OFFSET) &= ~1UL; // turn on main oscillator verify circuit
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}
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void sysclk_set_freq(uint8_t freq_id){
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uint32_t rcc1, rcc2=0;
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sysclk_set_rawclock();
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rcc1 = HW_REG(SYSCTL_BASE+RCC_OFFSET);
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// rcc2 = HW_REG(SYSCTL_BASE+RCC2_OFFSET);
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rcc1 &= ~(0x1f<<RCC_XTAL);
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rcc1 |= CRYSTAL_CODE<<RCC_XTAL;
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rcc2 = _BV(RCC2_USERCC2) | _BV(RCC2_PWRDN2) | _BV(RCC2_BYPASS2) | _BV(RCC2_USBPWRDN); /* OSCSRC2 is set to 0 */
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HW_REG(SYSCTL_BASE+RCC_OFFSET) = rcc1;
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HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
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rcc2 &= ~_BV(RCC2_PWRDN2);
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HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
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rcc2 |= _BV(RCC2_DIV400) | (freq_id<<RCC2_SYSDIV2LSB);
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HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
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while(!(HW_REG(SYSCTL_BASE+RIS_OFFSET)&_BV(RIS_PLLLRIS))){
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}
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// return;
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rcc2 &= ~_BV(RCC2_BYPASS2);
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HW_REG(SYSCTL_BASE+RCC2_OFFSET) = rcc2;
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}
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void sysclk_set_80MHz(void){
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sysclk_set_freq(SYS_FREQ_80MHZ000);
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}
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uint32_t sysclk_get_freq(void){
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uint32_t rcc1, rcc2, basefreq=400000000UL, divider=1;
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const uint32_t bypass_freq[] = {
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CRYSTAL_FREQ, PIOSC_FREQ, PIOSC_FREQ/4, 30000,
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0, 0, 4194304, 32768 };
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rcc1 = HW_REG(SYSCTL_BASE+RCC_OFFSET);
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rcc2 = HW_REG(SYSCTL_BASE+RCC2_OFFSET);
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if(rcc2&_BV(RCC2_USERCC2)){
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/* use RCC2 */
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if(rcc2&_BV(RCC2_BYPASS2)){
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basefreq = bypass_freq[(rcc2>>RCC2_OSCSR2)&0x07];
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}
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if(rcc2&_BV(RCC2_DIV400)){
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divider = ((rcc2>>RCC2_SYSDIV2LSB)&0x7F)+1;
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}else{
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divider = ((rcc2>>RCC2_SYSDIV2)&0x3F)+1;
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}
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}else{
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/* use RCC */
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if(rcc1&_BV(RCC_BYPASS)){
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basefreq = bypass_freq[(rcc1>>RCC_OSCSRC)&0x03];
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}
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divider = ((rcc1>>RCC_SYSDIV)&0xf)+1;
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}
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return basefreq/divider;
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}
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