big bug fixed, still some problems with flow control
This commit is contained in:
parent
a5cb349f9d
commit
7701e318e4
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@ -1,15 +0,0 @@
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The current version of the AVR-Crypto-Lib is BUGGY
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====================================================
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This is due to our afford of integrating newly optimized versions of the
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UART interface and the cli tools.
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We are working on this problem.
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Please use a revision prior to 2009-07-28.
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This means use
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svn revisions up to revision 2832 and
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bzr revisions up to revision 67
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best regards,
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Daniel Otte
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23
config.h
23
config.h
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@ -28,16 +28,6 @@
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#define DEBUG uart
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#define DEBUG uart
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/* uart.[ch] defines */
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#define UART_INTERRUPT 1
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#define UART_BAUD_RATE 38400
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#define UART_RXBUFSIZE 64
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#define UART_TXBUFSIZE 64
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#define UART_LINE_BUFFER_SIZE 40
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#define UART_XON_XOFF
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#define UART_XON_XOFF_THRESHOLD_1 (UART_RXBUFSIZE - 24)
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#define UART_XON_XOFF_THRESHOLD_2 (UART_RXBUFSIZE - 60)
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#undef UART_LEDS
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#undef UART_LEDS
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#define UART0_I 1
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#define UART0_I 1
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@ -47,19 +37,10 @@
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#define UART0_DATABITS UART_DATABITS_8
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#define UART0_DATABITS UART_DATABITS_8
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#define UART0_RXBUFFER_SIZE 64
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#define UART0_RXBUFFER_SIZE 64
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#define UART0_TXBUFFER_SIZE 64
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#define UART0_TXBUFFER_SIZE 64
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#define UART0_SWFLOWCTRL 1
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#define UART0_SWFLOWCTRL 0
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#define UART0_THRESH_LOW 10
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#define UART0_THRESH_LOW 10
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#define UART0_THRESH_HIGH 48
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#define UART0_THRESH_HIGH 48
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/*
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#define UART_HWFLOWCONTROL
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#define UART_RTS_PORT PORTA
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#define UART_RTS_DDR DDRA
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#define UART_CTS_PIN PINA
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#define UART_CTS_DDR DDRA
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#define UART_RTS_BIT 0
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#define UART_CTS_BIT 1
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*/
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//#define TWISTER_MUL_TABLE
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#define CLI_AUTO_HELP
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#define CLI_AUTO_HELP
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#endif
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#endif
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@ -229,6 +229,8 @@ circularbytebuffer_get_lifo:
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* }
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* }
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*
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*
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* param cb: r24:r25
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* param cb: r24:r25
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* return: r24
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* modifys: r22-r27,r30,r31
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*/
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*/
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.global circularbytebuffer_get_fifo
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.global circularbytebuffer_get_fifo
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circularbytebuffer_get_fifo:
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circularbytebuffer_get_fifo:
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@ -28,16 +28,6 @@
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#define DEBUG uart
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#define DEBUG uart
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/* uart.[ch] defines */
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#define UART_INTERRUPT 1
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#define UART_BAUD_RATE 38400
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#define UART_RXBUFSIZE 64
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#define UART_TXBUFSIZE 64
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#define UART_LINE_BUFFER_SIZE 40
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#define UART_XON_XOFF
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#define UART_XON_XOFF_THRESHOLD_1 (UART_RXBUFSIZE - 24)
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#define UART_XON_XOFF_THRESHOLD_2 (UART_RXBUFSIZE - 60)
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#undef UART_LEDS
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#undef UART_LEDS
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#define UART0_I 1
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#define UART0_I 1
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#define UART0_DATABITS UART_DATABITS_8
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#define UART0_DATABITS UART_DATABITS_8
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#define UART0_RXBUFFER_SIZE 64
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#define UART0_RXBUFFER_SIZE 64
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#define UART0_TXBUFFER_SIZE 64
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#define UART0_TXBUFFER_SIZE 64
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#define UART0_SWFLOWCTRL 1
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#define UART0_SWFLOWCTRL 0
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#define UART0_THRESH_LOW 10
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#define UART0_THRESH_LOW 10
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#define UART0_THRESH_HIGH 48
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#define UART0_THRESH_HIGH 48
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/*
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#define UART_HWFLOWCONTROL
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#define UART_RTS_PORT PORTA
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#define UART_RTS_DDR DDRA
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#define UART_CTS_PIN PINA
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#define UART_CTS_DDR DDRA
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#define UART_RTS_BIT 0
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#define UART_CTS_BIT 1
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*/
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//#define TWISTER_MUL_TABLE
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#define CLI_AUTO_HELP
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#define CLI_AUTO_HELP
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#endif
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#endif
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@ -144,6 +144,7 @@ int main (void){
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cli_rx = (cli_rx_fpt)uart0_getc;
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cli_rx = (cli_rx_fpt)uart0_getc;
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cli_tx = (cli_tx_fpt)uart0_putc;
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cli_tx = (cli_tx_fpt)uart0_putc;
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testrun_md5();
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for(;;){
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for(;;){
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cli_putstr_P(PSTR("\r\n\r\nCrypto-VS ("));
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cli_putstr_P(PSTR("\r\n\r\nCrypto-VS ("));
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cli_putstr(algo_name);
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cli_putstr(algo_name);
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@ -71,6 +71,25 @@
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# define RXC0 RXC
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# define RXC0 RXC
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# define TXB80 TXB8
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# define TXB80 TXB8
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# define RXB80 RXB8
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# define RXB80 RXB8
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# define U2X0 U2X
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# define UDRIE0 UDRIE
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# define RXCIE0 RXCIE
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#endif
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#ifdef USART0_RX_vect
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# define RX_ISR USART0_RX_vect
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#endif
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#ifdef USART_RXC_vect
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# define RX_ISR USART_RXC_vect
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#endif
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#ifdef USART0_UDRE_vect
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# define TX_ISR USART0_UDRE_vect
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#endif
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#ifdef USART_UDRE_vect
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# define TX_ISR USART_UDRE_vect
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#endif
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#endif
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#define CBB_SIZE 10
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#define CBB_SIZE 10
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clr r25
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clr r25
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ldi r22, lo8(uart0_ctx+UART0_CBB_RX_OFFSET)
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ldi r22, lo8(uart0_ctx+UART0_CBB_RX_OFFSET)
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ldi r23, hi8(uart0_ctx+UART0_CBB_RX_OFFSET)
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ldi r23, hi8(uart0_ctx+UART0_CBB_RX_OFFSET)
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ldi r24, UART0_RXBUFFER_SIZE
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ldi r20, lo8(uart0_rxbuffer)
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ldi r20, lo8(uart0_rxbuffer)
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ldi r21, hi8(uart0_rxbuffer)
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ldi r21, hi8(uart0_rxbuffer)
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rcall circularbytebuffer_init2
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rcall circularbytebuffer_init2
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clr r25
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clr r25
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ldi r22, lo8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r22, lo8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r23, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r23, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r24, UART0_TXBUFFER_SIZE
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ldi r20, lo8(uart0_txbuffer)
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ldi r20, lo8(uart0_txbuffer)
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ldi r21, hi8(uart0_txbuffer)
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ldi r21, hi8(uart0_txbuffer)
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rcall circularbytebuffer_init2
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rcall circularbytebuffer_init2
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@ -183,7 +200,6 @@ uart0_init:
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SET_BIT_IO UCSR0A, U2X0, r24
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SET_BIT_IO UCSR0A, U2X0, r24
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#else
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#else
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CLEAR_BIT_IO UCSR0A, U2X0, r24
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CLEAR_BIT_IO UCSR0A, U2X0, r24
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/* UCSR0A */
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#endif
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#endif
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ldi r24, (UART0_PARATY<<4)|(UART0_STOPBITS<<3)|((UART0_DATABITS&3)<<1)
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ldi r24, (UART0_PARATY<<4)|(UART0_STOPBITS<<3)|((UART0_DATABITS&3)<<1)
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STORE_IO UCSR0C, r24
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STORE_IO UCSR0C, r24
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* }
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* }
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*/
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*/
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.global USART0_UDRE_vect
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.global TX_ISR
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USART0_UDRE_vect:
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TX_ISR:
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push_range 21, 26
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push r1
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push_range 30, 31
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push r21
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push r22
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in r21, _SFR_IO_ADDR(SREG)
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in r21, _SFR_IO_ADDR(SREG)
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CLEAR_BIT_IO UCSR0B, UDRIE0, r22
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sei
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push_range 23, 27
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push_range 30, 31
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clr r1
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ldi r24, lo8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r24, lo8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r25, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r25, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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rcall circularbytebuffer_get_fifo
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rcall circularbytebuffer_get_fifo
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breq 30b
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breq 30b
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#endif
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#endif
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STORE_IO UDR0, r24
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STORE_IO UDR0, r24
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SET_BIT_IO UCSR0B, UDRIE0, r22
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99:
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99:
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ori r21, 0x80 /* set I bit */
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out _SFR_IO_ADDR(SREG), r21
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out _SFR_IO_ADDR(SREG), r21
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pop_range 30, 31
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pop_range 30, 31
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pop_range 21, 26
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pop_range 21, 27
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reti
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pop r1
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ret
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/******************************************************************************/
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/******************************************************************************/
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/*
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/*
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ldi r26, lo8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r26, lo8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r27, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r27, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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20:
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20:
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; sei
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movw r24, r26
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movw r24, r26
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; nop
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; nop
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cli
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rcall circularbytebuffer_cnt
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rcall circularbytebuffer_cnt
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sei
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cpi r24, UART0_TXBUFFER_SIZE
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cpi r24, UART0_TXBUFFER_SIZE
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breq 20b
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breq 20b
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movw r22, r26
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movw r22, r26
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* }
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* }
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*
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*
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*/
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*/
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.global USART0_RX_vect
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.global RX_ISR
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USART0_RX_vect:
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RX_ISR:
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push_range 0, 1
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push_range 0, 1
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push_range 16, 31
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push_range 16, 31
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in r18, _SFR_IO_ADDR(SREG)
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in r16, _SFR_IO_ADDR(SREG)
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clr r1
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LOAD_IO r24, UDR0
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LOAD_IO r24, UDR0
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#if UART0_SWFLOWCTRL
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#if UART0_SWFLOWCTRL
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ldi r26, lo8(uart0_ctx+UART0_TXON_OFFSET)
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ldi r26, lo8(uart0_ctx+UART0_TXON_OFFSET)
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ldi r23, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r23, hi8(uart0_ctx+UART0_CBB_TX_OFFSET)
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ldi r30, lo8(uart0_ctx+UART0_RXON_OFFSET)
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ldi r30, lo8(uart0_ctx+UART0_RXON_OFFSET)
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ldi r31, hi8(uart0_ctx+UART0_RXON_OFFSET)
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ldi r31, hi8(uart0_ctx+UART0_RXON_OFFSET)
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ld r16, Z
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ld r18, Z
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tst r16
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tst r18
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breq 60f
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breq 60f
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cpi r24, UART0_THRESH_HIGH+1
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cpi r24, UART0_THRESH_HIGH+1
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brlo 99f
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brlo 99f
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SET_BIT_IO UCSR0B, UDRIE0, r24
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SET_BIT_IO UCSR0B, UDRIE0, r24
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#endif /* UART0_SWFLOWCTRL */
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#endif /* UART0_SWFLOWCTRL */
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99:
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99:
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out _SFR_IO_ADDR(SREG), r18
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out _SFR_IO_ADDR(SREG), r16
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pop_range 16, 31
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pop_range 16, 31
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pop_range 0, 1
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pop_range 0, 1
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reti
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reti
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